The present invention generally relates to the fabrication of integrated circuits, and more particularly to a technique of fabricating a contact trench using a combination of an isotropic etching technique and an anisotropic etching technique.
In the field of semiconductor devices, active semiconductor devices such as, for example, a transistor may be formed on a front-end-of-line of a semiconductor wafer. A transistor may be, for example, a field-effect-transistor (FET) and more specifically may be a complementary metal-oxide-semiconductor (CMOS) FET.
Generally, after a transistor is formed, conductive contacts are formed to connect the middle-end-of-line or back-end-of-line to a source, drain, and/or gate of the transistor to make the transistor functional. With the continuous scaling down in device dimension in integrated circuitry, real estate for forming corresponding contacts is also scaling down. In order to accomplish high device packing density, smaller feature sizes are also required. The feature sizes may include, for example, the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various device structures.